The invention relates to a memory device, in particular to a DRAM, and a system having a memory device. Further, the invention relates to a method for operating a memory device.
In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between functional memory devices (e.g., PLAs, PALs, etc.), and table memory devices, e.g., ROM devices (ROM=Read Only Memory—in particular PROMs, EPROMs, EEPROMs, flash memories, etc.), and RAM devices (RAM=Random Access Memory—in particular, e.g., DRAMs and SRAMs).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later. In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist, e.g., of few, for instance 6, transistors, and in the case of DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element.
In the case of memory devices, in particular DRAM devices, the individual memory cells are—positioned side by side in a plurality of rows and columns—arranged in a rectangular matrix or a rectangular array for technological reasons.
In order to obtain a correspondingly high total storage capacity and/or to achieve a data read or write rate that is as high as possible, a plurality of, e.g., two, four or eight—substantially rectangular—individual arrays may be provided in one single DRAM device or chip instead of one single array.
In conventional graphic systems, e.g., graphic systems 2 according to the GDDR3 or GDDR4 standard such as, e.g., illustrated in FIG. 1, one or—alternatively—two independent DRAM devices 1a, 1b might be provided per channel. Further, several channels might be provided, for instance, four channels (whereby to each channel one or—alternatively—two independent DRAM devices might be associated). For sake of simplicity, only one single channel is illustrated in FIG. 1.
In order to separately access the DRAM devices 1a, 1b of a respective channel, Chip Select (CS) Signals (here: a first Chip Select Signal (CS0), and a second Chip Select Signal (CS1)) are provided at system level.
The Chip Select Signals (CS0, CS1) are driven by a controller 5 on respective non-shared, separate chip select command lines 3a, 3b connected with a respective first and second chip select pin of the controller 5.
The first Chip Select Signal (CS0) may be provided via the chip select command line 3a to a chip select pin of the first DRAM device 1a (but not to a respective chip select pin of the second DRAM device 1b), and the second Chip Select Signal (CS1) may be provided via the chip select command line 3b to the chip select pin of the second DRAM device 1b (but not to the respective chip select pin of the first DRAM device 1a).
As is further illustrated in FIG. 1, in the graphic system 2, a respective data bus 3c (DQ-bus), address bus 3d (ADD-bus), and command bus 3e (CMD-bus) are provided, each of the buses 3c, 3d, 3e connected with the controller 5, and each of the DRAM devices 1a, 1b (i.e., with respective data, address and command pins provided there).
To perform a write or read access, a particular predetermined sequence of instructions has to be run through:
For instance, first, a respective DRAM device (i.e., either the DRAM device 1a, or the DRAM device 1b) is selected by an appropriate Chip Select Signal.
Then, by means of a word line activate command (activate command (ACT)) a corresponding word line defined by the row address is activated in a respective memory bank of the selected DRAM device.
Subsequently—by means of a corresponding read or write command (RD or WT command)—it is initiated that the corresponding data—then exactly specified by the corresponding column address—is output (or read in).
Next—by means of a word line deactivate command (e.g., a precharge command (PRE command))—the corresponding word line is deactivated again, and the corresponding memory bank is prepared for the next word line activate command (ACT).
In order to further increase the performance of the DRAM devices 1a, 1b, the controller 5 may—after the output of a corresponding word line activate command (ACT command) and of a corresponding read (or write) command (RD (or WT) command)—leave the respective word line in an activated state (i.e. the corresponding word line deactivate command (PRE command)—for the time being—is inhibited).
If then—which is, from a statistic point of view, the case very frequently—next a memory cell is accessed which is assigned to the same word line as the memory cell that was accessed last, the output of a further word line activate command (ACT command) can be omitted. Instead, the controller 5 may directly output a corresponding read (or write) command (RD (or WT) command).
By shrinking the size of the DRAM devices 1a, 1b, the costs for a respective DRAM device 1a, 1b might be decreased. However, if the controller 5 is to remain unchanged (in particular, with regards to the two Chip Select Signals (CS0, CS1) provided by two separate chip select pins of the controller 5), still, two separate DRAM devices 1a, 1b are necessary. These separate DRAM devices 1a, 1b, e.g., have to be tested separately, have to be mounted in two separate housings, which both have to be soldered into the system 2, etc., etc. Hence, compared with a solution with one single DRAM device (single-chip-solution), still, the systems costs are relatively high.
For these or other reasons, there is a need for the present invention.